For high-performance complementary MOS (CMOS) transistors, channel profile and source/drain extension (lightly doped drain (LDD)) engineering may be used. Lowering band-to-band (B2B) gate edge diode leakage (GDL) which results in off-state current leakage is a challenge particularly for low leakage (e.g., ultra-low-leakage (ULL)) high voltage threshold (HVT) MOS transistors. Self-aligned pockets (or halos) using the gate stack for self-alignment implanted around the LDDs can improve GDL, with higher angle pocket implants resulting in lower GDL. However, the typical pocket implant angle is limited to about 20 to 30 degrees because of blocking by protruding masking photoresist and/or the adjacent gate electrode (e.g., a polysilicon gate).